ccppi/fft_led
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stabilise sample rate

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This commit is contained in:
Jonathan Wyss 2024-03-26 18:44:33 +01:00
parent 2e5be064bf
commit d994c95941
1 changed files with 17 additions and 10 deletions
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27
main.c
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@ -35,30 +35,32 @@ const float log_scale = 64./log(64./SCALE_FACTOR + 1.);
int msec; int msec;
uint16_t ticks;
ISR(TIMER1_OVF_vect) ISR(TIMER1_OVF_vect)
{ {
if(msec<100) if(ticks < 65000)
{ {
msec++; ticks++;
} }
else msec=0; if(ticks > 65000)
{
ticks=0;
}
} }
int main (void) int main (void)
{ {
int i,i2; int i,i2;
//int colorb;
//int colora;
int sum,avg; int sum,avg;
char sample[64]; char sample[64];
//char im[64];
char buff[64]; char buff[64];
float fac_r=0.1; float fac_r=0.1;
float fac_g=0.1; float fac_g=0.1;
float fac_b=1; float fac_b=1;
msec=0; msec=0;
ticks=0;
struct cRGB led_bar1[8]; struct cRGB led_bar1[8];
//DDRB = (1<<mic);//would be setting output, default is input so no need for setting //DDRB = (1<<mic);//would be setting output, default is input so no need for setting
setupADC(); setupADC();
@ -81,9 +83,11 @@ int main (void)
{ {
//######RECORD SAMPLES###### //######RECORD SAMPLES######
sum = 0; sum = 0;
ticks=0;
for(i=0;i<64;i++) for(i=0;i<64;i++)
{ {
msec=0;
STARTADC; STARTADC;
sample[i] = (ADCH-128); //read Analog value register 8bit center -128 sample[i] = (ADCH-128); //read Analog value register 8bit center -128
//sample[i] = (sample[i] <= NOISE) ? 0 : (sample[i] - NOISE); //noise reduction //sample[i] = (sample[i] <= NOISE) ? 0 : (sample[i] - NOISE); //noise reduction
@ -91,8 +95,10 @@ int main (void)
// //
sum+=sample[i];//dc-bias sum+=sample[i];//dc-bias
//while(msec<=1);
} }
//samplingrate -> 1/ca30'000'00r
avg = sum/64;//calculate bias avg = sum/64;//calculate bias
for(i=0;i<64;i++) for(i=0;i<64;i++)
{ {
@ -139,6 +145,7 @@ int main (void)
} }
} }
ws2812_setleds(led_bar1,8); ws2812_setleds(led_bar1,8);
while(ticks<60){ asm("");}//workaround for stoping gcc optimizing
} }
return 0; return 0;
} }
@ -148,7 +155,7 @@ return 0;
void setupTimer(void) void setupTimer(void)
{ {
clock_prescale_set(0); clock_prescale_set(0);
TCCR1 = (1<<CS10);//(1<<CS13)|(1<<CS10)|(1<<CTC1); //clear timer on compare match TCCR1 = (1<<CS10);//|(1<<CS10)|(1<<CTC1); /8 //clear timer on compare match
GTCCR = 0; //default values should be ok GTCCR = 0; //default values should be ok
//OCR1C = 117; //Compare value of timer / overflow , sets OCF1A //OCR1C = 117; //Compare value of timer / overflow , sets OCF1A
//OCR1A = 117; //OCR1A = 117;