Correct Clockspeed #1

Closed
opened 2024-03-01 07:49:08 +00:00 by ccppi · 2 comments
Owner

-Makefile
-correct adc samplingrate

-Makefile -correct adc samplingrate
Author
Owner

125ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013

By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz
to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can
be higher than 200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency
than 1 MHz.

125ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency than 1 MHz.
Author
Owner

But it works, well with 8 bit resolution, even with overclock.

But it works, well with 8 bit resolution, even with overclock.
ccppi closed this issue 2024-03-05 09:58:10 +00:00
Sign in to join this conversation.
No Label
No Milestone
No project
No Assignees
1 Participants
Notifications
Due Date
The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: ccppi/fft_led#1
No description provided.