From 0894b6aac56636fa596c30aab303524d869364ad Mon Sep 17 00:00:00 2001
From: Jonathan Wyss <j.wyss@kolabnow.ch>
Date: Wed, 6 Mar 2024 12:28:34 +0100
Subject: [PATCH] attiny45

---
 main.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/main.c b/main.c
index 9c20380..05fc130 100644
--- a/main.c
+++ b/main.c
@@ -4,7 +4,7 @@
 #include <avr/interrupt.h>
 
 #define PATTERN_COUNT 4
-
+#define attiny45
 typedef struct
 {
 	unsigned char r;
@@ -17,10 +17,7 @@ volatile int  counts;
 
 
 
-ISR(TIMER0_OVF_vect)
-{
-		count();
-}
+
 void count(void)
 {
 	//counts=0;//0..65535 
@@ -39,7 +36,10 @@ void count(void)
 	}
 
 }
-
+ISR(TIMER0_OVF_vect)
+{
+		count();
+}
 
 
 
@@ -67,7 +67,7 @@ int main (void) {            // (2)
 	DDRB = (1 << PB0 )|(1<<PB1)|(1<<PB4);
 	cli();
 //#######Timer0-setup#####			|Phase correct pwm
-	TCCR0A = (1<<COM0A1)|(1<<COM0B1)|(1<<WGM00)|(1<<WGM00);	//mode
+	TCCR0A = (1<<COM0A1)|(1<<COM0B1)|(1<<WGM00)|(1<<WGM01);	//mode fast pwm (1/Fcpu)*prescaler*(max+1) = 
 	TCCR0B = (1<<CS00)|(1<<CS00);				//frequency /256 = 31250Hz , 1 t0 period = 8.192ms 1 increment = 0.032ms strangly prescaler of 1 results in expected results as prescaler was 256
 
 //	PLLCSR |= (1 << PLLE) | (1 << PCKE);
@@ -151,7 +151,6 @@ sei();
 				pre_delay = ms;		
 			//	:wq
 			while((ms-pre_delay) < pattern[i2][i+1].time_hold){};
-
 	  	if(r == pattern[i2][i+1].r && g == pattern[i2][i+1].g && b == pattern[i2][i+1].b) break;
 		}
 	   }