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attiny45

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This commit is contained in:
Jonathan Wyss 2024-03-06 12:28:34 +01:00
parent 2fd404f14d
commit 0894b6aac5
1 changed files with 7 additions and 8 deletions
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15
main.c
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@ -4,7 +4,7 @@
#include <avr/interrupt.h> #include <avr/interrupt.h>
#define PATTERN_COUNT 4 #define PATTERN_COUNT 4
#define attiny45
typedef struct typedef struct
{ {
unsigned char r; unsigned char r;
@ -17,10 +17,7 @@ volatile int counts;
ISR(TIMER0_OVF_vect)
{
count();
}
void count(void) void count(void)
{ {
//counts=0;//0..65535 //counts=0;//0..65535
@ -39,7 +36,10 @@ void count(void)
} }
} }
ISR(TIMER0_OVF_vect)
{
count();
}
@ -67,7 +67,7 @@ int main (void) { // (2)
DDRB = (1 << PB0 )|(1<<PB1)|(1<<PB4); DDRB = (1 << PB0 )|(1<<PB1)|(1<<PB4);
cli(); cli();
//#######Timer0-setup##### |Phase correct pwm //#######Timer0-setup##### |Phase correct pwm
TCCR0A = (1<<COM0A1)|(1<<COM0B1)|(1<<WGM00)|(1<<WGM00); //mode TCCR0A = (1<<COM0A1)|(1<<COM0B1)|(1<<WGM00)|(1<<WGM01); //mode fast pwm (1/Fcpu)*prescaler*(max+1) =
TCCR0B = (1<<CS00)|(1<<CS00); //frequency /256 = 31250Hz , 1 t0 period = 8.192ms 1 increment = 0.032ms strangly prescaler of 1 results in expected results as prescaler was 256 TCCR0B = (1<<CS00)|(1<<CS00); //frequency /256 = 31250Hz , 1 t0 period = 8.192ms 1 increment = 0.032ms strangly prescaler of 1 results in expected results as prescaler was 256
// PLLCSR |= (1 << PLLE) | (1 << PCKE); // PLLCSR |= (1 << PLLE) | (1 << PCKE);
@ -151,7 +151,6 @@ sei();
pre_delay = ms; pre_delay = ms;
// :wq // :wq
while((ms-pre_delay) < pattern[i2][i+1].time_hold){}; while((ms-pre_delay) < pattern[i2][i+1].time_hold){};
if(r == pattern[i2][i+1].r && g == pattern[i2][i+1].g && b == pattern[i2][i+1].b) break; if(r == pattern[i2][i+1].r && g == pattern[i2][i+1].g && b == pattern[i2][i+1].b) break;
} }
} }