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2 Commits
attiny45 ... main

Author SHA1 Message Date
ccppi
6ccdeb6cf0 Cosmetics 2024-03-14 21:25:20 +00:00
ccppi
e0db62d3f5 Remove spaces, rearange tabs 2024-03-14 21:21:59 +00:00
1 changed files with 47 additions and 72 deletions
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main.c
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@ -15,8 +15,6 @@ typedef struct
volatile uint16_t ms; volatile uint16_t ms;
volatile int counts; volatile int counts;
ISR(TIMER0_OVF_vect) ISR(TIMER0_OVF_vect)
{ {
count(); count();
@ -37,21 +35,16 @@ void count(void)
ms=0; ms=0;
} }
} }
} }
int main (void)
{
int main (void) { // (2)
rgbval pattern[6][PATTERN_COUNT]={ {{0,0,0,10}, {0,0,0,10}, {0,0,0,10}, {0,0,0,10}}, rgbval pattern[6][PATTERN_COUNT]={ {{0,0,0,10}, {0,0,0,10}, {0,0,0,10}, {0,0,0,10}},
{{1,1,1,10}, {1,1,153,20}, {200,50,39,10}, {204,255,153,20}}, {{1,1,1,10}, {1,1,153,20}, {200,50,39,10}, {204,255,153,20}},
{{1,1,1,10}, {10,255,0,10}, {1,1,255,20}, {1,200,1,20}}, {{1,1,1,10}, {10,255,0,10}, {1,1,255,20}, {1,200,1,20}},
{{1,1,5,10}, {1,1,255,10}, {1,1,5,10}, {1,1,255,10}}, {{1,1,5,10}, {1,1,255,10}, {1,1,5,10}, {1,1,255,10}},
{{252,102,3,10}, {161,67,47,10}, {118,120,74,10}, {83,120,74,20}}, {{252,102,3,10}, {161,67,47,10}, {118,120,74,10}, {83,120,74,20}},
{{87,119,122,10}, {95,87,122,10}, {52, 69, 56,10}, {83, 84, 72,10}}}; {{87,119,122,10}, {95,87,122,10}, {52, 69, 56,10}, {83, 84, 72,10}}};
//rgbval *pattern=pattern1[0];
int i=0,i2=0,i3; int i=0,i2=0,i3;
int r,g,b = 0; int r,g,b = 0;
int set=0; int set=0;
@ -59,7 +52,6 @@ int main (void) { // (2)
uint16_t pre_delay=0; uint16_t pre_delay=0;
ms =0; ms =0;
counts = 0; counts = 0;
//disable prescaler //disable prescaler
CLKPR = (1<<CLKPR); CLKPR = (1<<CLKPR);
CLKPR = 0x00; CLKPR = 0x00;
@ -69,31 +61,27 @@ int main (void) { // (2)
//#######Timer0-setup##### |Phase correct pwm //#######Timer0-setup##### |Phase correct pwm
TCCR0A = (1<<COM0A1)|(1<<COM0B1)|(1<<WGM00)|(1<<WGM00); //mode TCCR0A = (1<<COM0A1)|(1<<COM0B1)|(1<<WGM00)|(1<<WGM00); //mode
TCCR0B = (1<<CS00)|(1<<CS00); //frequency /256 = 31250Hz , 1 t0 period = 8.192ms 1 increment = 0.032ms strangly prescaler of 1 results in expected results as prescaler was 256 TCCR0B = (1<<CS00)|(1<<CS00); //frequency /256 = 31250Hz , 1 t0 period = 8.192ms 1 increment = 0.032ms strangly prescaler of 1 results in expected results as prescaler was 256
// PLLCSR |= (1 << PLLE) | (1 << PCKE); // PLLCSR |= (1 << PLLE) | (1 << PCKE);
//######Timer1-setup //######Timer1-setup
TCCR1 = (1<<COM1A0)|(1<<COM1A1)|(1<<CTC1)|(1<<CS12)|(1<<CS10);//|(1<<CS11)|(1<<CS13); //frequencyi //iinverting PWM because 0 dtc not possible TCCR1 = (1<<COM1A0)|(1<<COM1A1)|(1<<CTC1)|(1<<CS12)|(1<<CS10);//|(1<<CS11)|(1<<CS13); //frequencyi //iinverting PWM because 0 dtc not possible
GTCCR = (1<<PWM1B)|(1<<COM1B0); //mode + overrun clear, Set on compare match GTCCR = (1<<PWM1B)|(1<<COM1B0); //mode + overrun clear, Set on compare match
OCR1C = 255; // clear timer at 255 OCR1C = 255; // clear timer at 255
//######PWM_VALUE$ //######PWM_VALUE$
//timer 0 //timer 0
OCR0A = 1; OCR0A = 1;
OCR0B = 1; OCR0B = 1;
//timer 1 //timer 1
OCR1B = 1; OCR1B = 1;
//######Configure Pullups //######Configure Pullups
PORTB |= (1<<PB2); PORTB |= (1<<PB2);
//Interupts
//enable global interrupts
//Interupts
TIMSK |= (1<<TOIE0);//interrupt on overflow = one timer cycle TIMSK |= (1<<TOIE0);//interrupt on overflow = one timer cycle
TIFR |= (1<<TOV0); TIFR |= (1<<TOV0);
TCNT0 = 0; TCNT0 = 0;
sei(); //enable global interrupts
sei();
while(1) while(1)
{ {
for(i=1;i<PATTERN_COUNT;i++) for(i=1;i<PATTERN_COUNT;i++)
{ {
r = pattern[i2][i].r; r = pattern[i2][i].r;
@ -115,7 +103,6 @@ sei();
i2=0; i2=0;
} }
//cycle through and stop pwm at value 0 //cycle through and stop pwm at value 0
//Visual feedback "mode change" //Visual feedback "mode change"
for(i3=0;i3<i2;i3++) for(i3=0;i3<i2;i3++)
{ {
@ -130,34 +117,22 @@ sei();
set=0; set=0;
} }
//Pattern handling //Pattern handling
if(r < pattern[i2][i+1].r) {r++;} if(r < pattern[i2][i+1].r) {r++;}
if(r > pattern[i2][i+1].r) {r--;} if(r > pattern[i2][i+1].r) {r--;}
if(g < pattern[i2][i+1].g) {g++;} if(g < pattern[i2][i+1].g) {g++;}
if(g > pattern[i2][i+1].g) {g--;} if(g > pattern[i2][i+1].g) {g--;}
if(b < pattern[i2][i+1].b) {b++;} if(b < pattern[i2][i+1].b) {b++;}
if(b > pattern[i2][i+1].b) {b--;} if(b > pattern[i2][i+1].b) {b--;}
OCR0A = g;//green OCR0A = g;//green
OCR0B = r;//red OCR0B = r;//red
OCR1B = b;//blue OCR1B = b;//blue
// :wq
// _delay_ms(10); // _delay_ms(10);
pre_delay = ms; pre_delay = ms;
// :wq
while((ms-pre_delay) < pattern[i2][i+1].time_hold){}; while((ms-pre_delay) < pattern[i2][i+1].time_hold){};
if(r == pattern[i2][i+1].r && g == pattern[i2][i+1].g && b == pattern[i2][i+1].b) break; if(r == pattern[i2][i+1].r && g == pattern[i2][i+1].g && b == pattern[i2][i+1].b) break;
} }
} }
} }
return 0; return 0;
} }